The present invention is described for achieving a reduced length of a polysilicon structure used as a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, the present invention may be used for fabrication of a polysilicon structure having a reduced length that is beyond photolithography limitations for any other type of application aside from just the example of a gate electrode of a MOSFET, as would be apparent to one of ordinary skill in the art from the description herein.
MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are a common component of integrated circuits. A typical MOSFET includes a drain, a source, a gate dielectric, and a gate electrode as known to one of ordinary skill in the art of integrated circuits. The gate electrode is comprised of a conductive material and is disposed to abut the gate dielectric. Polysilicon is commonly used as the gate electrode of a MOSFET.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
For improved performance of a MOSFET, the length of the gate electrode is further scaled down. As known to one of ordinary skill in the art, photolithography technology is commonly used for defining the size and shape of the gate electrode of a MOSFET in an integrated circuit. However, a bottleneck for further scaling down of the gate electrode of a MOSFET is the limitation of photolithography technology from optical diffraction, as known to one of ordinary skill in the art of integrated circuit fabrication. In current photolithography technology using UV (Ultra-Violet) or deep UV (Ultra-Violet) light as the illumination source for example, gate lengths that are smaller than 0.1 .mu.m may not be achieved because of optical diffraction.
A prior art technology for achieving MOSFET gate lengths that are beyond those achievable from photolithography technology is photoresist trimming. In this prior art technology, the photoresist layer used in a typical photolithography process is further etched down to smaller dimensions to achieve smaller device size. However, the size and shape of a structure fabricated using photoresist trimming may be difficult to control, as known to one of ordinary skill in the art of integrated circuit fabrication.
Thus, a method for fabricating a gate electrode with controllable reduced gate lengths that are beyond those achievable from photolithography technology is desired.